Since the quad connected to the optical module on the vc709 development board does not have a direct input reference clock, but is connected to a pair of SMA interfaces, we output the clock generated by the 156.25mhz crystal oscillator to another pair of SMA interfaces after being driven by ibufds and obufds inside the FPGA, and interconnect the two pairs of SMA interfaces through coaxial cable, so that the quad connected to the optical module has an input reference clock. The specific clock layout is shown in Figure 5.3. Therefore, our clock layout needs to fully consider the structure of this development board. In this paper, Xilinx vc709 development board is selected as the hardware platform for on-board debugging. Clock layout design of 10G Ethernet interfaceĪs 10G Ethernet PCS / PMA is an IP core officially provided by Xilinx, what we need to do is to design a reasonable clock circuit for this IP core and other modules in combination with the actual situation of the development board to make it work normally. PMA proximal loop is used to test the internal self loop of IP core PMA remote loopback is used to directly loopback the received data sent by the remote 10g PHY to the remote 10g PHY at the PMA layer without passing through the local PCs layer.ģ. In the process of interface debugging, the near end loopback and far end loopback functions of PMA layer may be used.
At the same time, the test excitation detection function is also provided in the test mode to detect the working state of the link. PCs layer performs block synchronization, descrambling code, 64b / 66b decoding, elastic cache and other functions for the data received from PMA layer.
#10g mac ethernet project serial
For the received data, the main functions of PMA layer are serial parallel conversion, bit synchronization, clock recovery and other functions of the received high-speed differential signal. The main function of PMA layer is to provide parallel serial conversion, drive and send serial signals and other functions. At the same time, a test excitation source is also provided in the test mode to detect the link. For sending data, the main functions of PCs layer are 64b / 66b coding, scrambling, transmission speed change and other functions of data. As can be seen from the figure, the module is divided into PCs layer and PMA layer. The overall structure of 10G Ethernet PCS / PMA is shown in Figure 5.2, and its core is implemented based on rocketio GTH / GTX. It should be noted that this design mainly completes the logic design of Ethernet layer 2, and does not involve the logic design of PHY layer, such as bit synchronization, byte synchronization, word synchronization, 64b / 66b codec, etc. In this design, 10gethernet PCS / PMA IP core provided by Xilinx company is used as the PHY chip connecting 10gmac, and then the IP core is constrained to the optical module to build a complete physical layer. This paper will introduce the principle and debugging technology of 10G Ethernet interface based on FPGA in detail.ġ0G Ethernet interface is divided into 10g phy and 10g Mac.
The higher speed Ethernet interface technology is the key of application. With the acceleration of FPGA in data center and the wide application of smart NIC in SDN and nfv, FPGA development board based on Ethernet interface has attracted more and more attention.
0 kommentar(er)
